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ADE7769
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V DD 1
V2P 2
16
15
F1
F2
V2N 3
ADE7769
14
CF
V1N 4
TOP VIEW
13 DGND
V1P 5 (Not to Scale) 12 REVP
AGND 6
REF IN/OUT 7
SCF 8
11
10
9
RCLKIN
S0
S1
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2, 3
4, 5
6
7
8
9, 10
11
12
13
14
15, 16
Mnemonic
V DD
V2P, V2N
V1N, V1P
AGND
REF IN/OUT
SCF
S1, S0
RCLKIN
REVP
DGND
CF
F2, F1
Description
Power Supply. This pin provides the supply voltage for the circuitry in the ADE7769. The supply voltage
should be maintained at 5 V ± 5% for specified operation. This pin should be decoupled with a 10 μF
capacitor in parallel with a 100 nF ceramic capacitor.
Analog Inputs for Channel V2 (Voltage Channel). These inputs provide a fully differential input pair. The
maximum differential input voltage is ±165 mV for specified operation. Both inputs have internal ESD
protection circuitry; an overvoltage of ±6 V can be sustained on these inputs without risk of permanent
damage.
Analog Inputs for Channel V1 (Current Channel). These inputs are fully differential voltage inputs with a
maximum signal level of ±30 mV with respect to the V1N pin for specified operation. Both inputs have
internal ESD protection circuitry and, in addition, an overvoltage of ±6 V can be sustained on these inputs
without risk of permanent damage.
This pin provides the ground reference for the analog circuitry in the ADE7769, that is, the ADCs and
reference. This pin should be tied to the analog ground plane of the PCB. The analog ground plane is the
ground reference for all analog circuitry, such as antialiasing filters, current and voltage sensors, and so forth.
For accurate noise suppression, the analog ground plane should be connected to the digital ground plane at
only one point. A star ground configuration helps to keep noisy digital currents away from the analog
circuits.
This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of 2.45 V
and a typical temperature coefficient of 20 ppm/°C. An external reference source may also be connected at
this pin. In either case, this pin should be decoupled to AGND with a 1 μF tantalum capacitor and a 100 nF
ceramic capacitor. The internal reference cannot be used to drive an external load.
Select Calibration Frequency. This logic input is used to select the frequency on the calibration output CF. See
Table 7.
These logic inputs are used to select one of four possible frequencies for the digital-to-frequency conversion.
With this logic input, designers have greater flexibility when designing an energy meter. See the Selecting a
Frequency for an Energy Meter Application section.
To enable the internal oscillator as a clock source to the chip, a precise low temperature drift resistor at a
nominal value of 6.2 kΩ must be connected from this pin to DGND.
This logic output goes high when negative power is detected, that is, when the phase angle between the
voltage and current signals is greater than 90°. This output is not latched and is reset when positive power is
once again detected. The output goes high or low at the same time that a pulse is issued on CF.
This pin provides the ground reference for the digital circuitry in the ADE7769, that is, the multiplier, filters,
and digital-to-frequency converter. This pin should be tied to the digital ground plane of the PCB. The digital
ground plane is the ground reference for all digital circuitry, such as the counters (mechanical and digital),
MCUs, and indicator LEDs. For accurate noise suppression, the analog ground plane should be connected to
the digital ground plane at one point only—a star ground.
Calibration Frequency Logic Output. The CF logic output provides instantaneous real power information. This
output is intended for calibration purposes. See the SCF pin description. This output stays high when the part
is in a no-load condition.
Low Frequency Logic Outputs. F1 and F2 supply average real power information. The logic outputs can be
used to directly drive electromechanical counters and 2-phase stepper motors. See the Transfer Function
section.
Rev. A | Page 7 of 20
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